 |
 |
 |
 |
 |
 |
New PCI Express Available on General Standards' Analog, Serial, and Digital I/O Boards
PCI Express, officially abbreviated as PCIe is a computer expansion card interface format. It was designed as a much faster interface to replace PCI, PCIX, and AGP interfaces for computer expansion cards and graphics cards. The PCI Express (PCIe) physical connection (slot) is completely different from those of the older standard PCI slots or those for PCI Extended (PCIX).
PCIe is a technology which is receiving further development and improvement. The initial standard version in general use is PCIe 1.1; however, PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. PCIe 2.0 doubles the data rate of each lane from 250 MB/s to 500 MB/s. PCIe 2.0 is still compatible with PCIe 1.1 as a physical interface slot and from within software, so older cards will still be able to work in machines fitted with this new version. Further information on PCIe 2.0 is detailed below.
PCIe is backwards-compatible with PCI, and operating systems can boot on and use a PCIe-based system without modification.
Features:
A single PCI Express serial link is a dual-simplex connection using two pairs of wires, one pair for transmit and one pair for receive, and can only transmit one bit per cycle. Although this sounds limiting, it can transmit at the extremely high speed of 2.5 Gbps, which equates to a burst mode of 320 MBps on a single connection. These two pairs of wires is called a lane.
You can install PCI Express adapters in larger slots but not smaller ones. For example, you can install a PCI Express x1 adapter into an x16 slot (but will still operate at the x1 speed), but you cannot insert an x16 adapter into anx1 slot. This compatibility is shown in Table 5.3* below.
PCI Express currently runs at 2.5 Gbps, or 200 MBps per lane in each direction, providing a total bandwidth of 80 Gbps in a 32-lane configuration, and up to 160 Gbps in a full duplex x32 configuration.
Future frequency increases will scale up total bandwidth to the limits of copper (which is 12.5 Gbps per wire) and significantly beyond that via other media without impacting any layers above the physical layer in the protocol stack. The table below shows the throughput of PCI Express at different lane widths.
*Table 5.3: PCI Express maximum transfer rate Lane width Clock speed Throughput (duplex, bits) Throughput (duplex, bytes) Initial expected uses:
x1 2.5 GHz 5 Gbps 400 MBps Slots, Gigabit Ethernet
x2 2.5 GHz 10 Gbps 800 MBps
x4 2.5 GHz 20 Gbps 1.6 GBps Slots, 10 Gigabit Ethernet, SCSI, SAS
x8 2.5 GHz 40 Gbps 3.2 GBps
x16 2.5 GHz 80 Gbps 6.4 GBps Graphics adapters
PCI Express uses an embedded clocking technique using 8b/10b encoding. The clock information is encoded directly into the data stream, rather than having the clock as a separate signal. The 8b/10b encoding essentially requires 10 bits per character, or about 20% channel overhead. This encoding explains differences in the published spec speeds of 250 MBps (with the embedded clock overhead) and 200 MBps (data only, without the overhead). For ease of comparison, Table 5-3 shows throughput in both bps and Bps.
Any PMC I/O board can be used on PCI Express, PCI-X, cPCI-X, PCI, cPCI, PC-104-Plus via an adapter. Our I/O boards are being converted to PCI Express boards as opportunities arise. View our extensive line of I/O boards.
We also have several drivers available, including VxWorks, Linux, and Windows 2000. Call for availability or requests at (800) 653-9970.
(800) 653-9970
www.generalstandards.com
For more information on these products, click on the following links:
PCIe: http://www.generalstandards.com/pciexpress.php
For more information on Drivers, go to:
Linux: http://www.generalstandards.com/linux.php